The open collector outputs of two 2-inputs NAND gates are connected to a common pull up resistor. If the input to the gates are P, Q and R, S respectively, the output is equal to
`bar(P.Q)` . `bar(R.S.)`
`bar(PQ)` + `bar(RS)`
``P.Q + R.S
P.Q . R.S
Why... please help